A Flash memory permits stored data to be retained even if power to the memory is removed. A Flash memory cell stores data either by storing electrical charge in an electrically isolated floating gate of a field effect transistor (FET) or by storing electrical charge in a dielectric layer underlying a control gate of a FET. The stored electrical charge controls the threshold of the FET, thereby controlling the memory state of the Flash memory cell.
A Flash memory cell is commonly programmed using hot carrier injection to inject charge carriers either onto a floating gate or into charge trapping sites in a dielectric layer underlying a control, gate. High drain and gate voltages are used to speed up the programming process. Thus, the Flash memory cell conducts a high current during programming, which is undesirable in low voltage and low power applications.
A split-gate cell is a type of Flash memory cell, in which a select gate is placed adjacent a memory gate, providing lower current during hot-carrier-based programming operation. During the programming of the split-gate cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since the acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate above that region results in more efficient carrier acceleration in the horizontal direction compared to the conventional memory cell. That makes the hot-carrier injection more efficient with lower current and lower power consumption during the programming operation. A split-gate cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional Flash memory cell during the programming operation may vary.
Fast read time is another advantage of the split-gate cell. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erase state at or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between the erased and the programmed states. The resulting voltages applied to both the select gate and the memory gate in read operation are less than or equal to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
It is also becoming increasingly common to monolithically incorporate multiple field-effect devices on the same substrate as the memory cells to provide improved efficiency, security, functionality, and reliability. As such, many processes are tailored in order to conform with standard CMOS fabrication. For example, a chip with split-gate cells may also include other field-effect devices to perform various logic and power control processes.
These other field-effect devices may include transistors tailored for high speed operation, while other transistors are tailored for handling higher-than-normal operating voltages. However, incorporating both on the same substrate along with the split-gate cell is challenging as each requires different fabrication parameters. Accordingly, there is a need for device and methods for integrating these split-gate cells and other field-effect devices with improved performance, cost, and manufacturability.